View MC14094BCPNBSP_278559.PDF datasheet online --- IC-ON-LINE

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MC14094B 8-Stage Shift/Store Register with Three-State Outputs
The MC14094B combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high-speed cascaded systems. The QS output data is shifted on the following negative clock transition for use in low-speed cascaded systems. Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high. Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable.
http://onsemi.com MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 MC14094BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week MC14094B ALYW 14 094B ALYW 14094B AWLYWW
* Three-State Outputs * Capable of Driving Two Low-Power TTL Loads or One Low-Power * Input Diode Protection * Data Latch * Dual Outputs for Data Out on Both Positive and * *
Negative Clock Transitions Useful for Serial-to-Parallel Data Conversion Pin-for-Pin Compatible with CD4094B Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW
ORDERING INFORMATION
C C C Device MC14094BCP MC14094BD MC14094BDR2 MC14094BDT MC14094BDTR2 MC14094BF Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOEIAJ-16 Shipping 2000/Box 48/Rail 2500/Tape & Reel 96/Rail 2500/Tape & Reel See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
(c) Semiconductor Components Industries, LLC, 2000
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
1
AUGUST, 2000 - Rev. 4
Publication Order Number: MC14094B/D
MC14094B
PIN ASSIGNMENT
STROBE DATA CLOCK Q1 Q2 Q3 Q4 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD OUTPUT ENABLE Q5 Q6 Q7 Q8 QS QS
Clock
Output Enable 0 0 1 1 1 1
Parallel Outputs Strobe X X 0 1 1 1 Data X X X 0 1 1 Q1 Z Z No Chg. 0 1 No Chg. QN Z Z No Chg. QN-1 QN-1 No Chg.
Serial Outputs QS * Q7 No Chg. Q7 Q7 Q7 No Chg. QS No Chg. Q7 No Chg. No Chg. No Chg. Q7
Z = High Impedance
X = Don't Care
* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.
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4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
3-State Output Leakage Current
Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
ITL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
15
--
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- --
MC14094B
- 55_C
3 0.1 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 3.5 7.0 11 IT = (4.1 A/kHz) f + IDD IT = (14 A/kHz) f + IDD IT = (140 A/kHz) f + IDD -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 0.0001 Typ (4.) - 4.2 - 0.88 - 2.25 - 8.8 0.005 0.010 0.015 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- -- 125_C 3.0 1.0 0.05 0.05 0.05 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MaxIII Unit mAdc mAdc Adc Adc Adc Vdc Vdc Vdc Vdc A pF
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7. The formulas given are for the typical characteristics only at 25_C. 8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Strobe Pulse Width
Clock Pulse Frequency
Clock Rise and Fall Time
Clock Pulse Width, High
Hold Time Clock to Data
Setup Time Data in to Clock
Propagation Delay Time Clock to Serial out QS tPLH, tPHL = (0.90 ns/pF) CL + 305 ns tPLH, tPHL = (0.36 ns/pF) CL + 107 ns tPLH, tPHL = (0.26 ns/pF) C L + 82 ns
Output Rise and Fall Time tTLH, tTHL = (1.35 ns/pF) CL + 33 ns tTLH, tTHL = (0.6 ns/pF) CL + 20 ns tTLH, tTHL = (0.4 ns/pF) CL + 20 ns
Output Enable to Output tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns ( ) tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns
Strobe to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 245 ns tPLH, tPHL = (0.36 ns/pF) C L + 127 ns tPLH, tPHL = (0.26 ns/pF) CL + 87 ns ( )
Clock to Parallel out tPLH, tPHL = (0.90 ns/pF) CL + 375 ns tPLH, tPHL = (0.35 ns/pF) CL + 177 ns tPLH, tPHL = (0.26 ns/pF) CL + 122 ns
Clock to Serial out Q'S tPLH, tPHL = (0.90 ns/pF) CL + 350 ns tPLH, tPHL = (0.36 ns/pF) CL + 149 ns tPLH, tPHL = (0.26 ns/pF) CL + 62 ns
tPLZ, tPZH = (0.90 ns/pF) CL + 180 ns tPLZ, tPZH = (0.36 ns/pF) CL + 77 ns tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns
Characteristic
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Symbol
MC14094B
tPHZ, tPZL
tPLH, tPHL
tTLH, tTHL
tPLZ, tPZH
tr(cl) tf(cl)
tWH
tWL
tsu
fcl
th
4 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5 10 15 Min 200 80 70 200 100 83 125 55 35 0 20 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (8.) - 40 - 10 0 100 40 35 100 50 40 225 95 70 140 75 55 290 145 100 420 195 135 230 110 75 350 125 95 100 50 40 2.5 5.0 6.0 60 30 20 -- -- -- 1.25 2.5 3.0 Max 450 190 140 280 150 110 580 290 200 840 390 270 460 220 150 600 250 190 200 100 80 15 5.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- MHz Unit s ns ns ns ns ns ns
MC14094B
3-STATE TEST CIRCUIT
FOR tPHZ AND tPZH VSS FOR tPLZ AND tPZL VDD
O.E. DATA ST CLOCK
1k OUTPUT 50 pF
BLOCK DIAGRAM
REGISTER STAGE 1 CLOCK 2 CLOCK LATCH 1 STROBE 3-STATE BUFFER 1 VDD 4 Q1
*
SERIAL DATA IN CLOCK CLOCK STROBE STROBE
CLOCK 15
CLOCK
STROBE
*
OUTPUT ENABLE 2 3 4 5 6 7 REGISTER STAGE 2 REGISTER STAGE 3 REGISTER STAGE 4 REGISTER STAGE 5 REGISTER STAGE 6 REGISTER STAGE 7 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 3-STATE BUFFER 2 3-STATE BUFFER 3 3-STATE BUFFER 4 3-STATE BUFFER 5 3-STATE BUFFER 6 3-STATE BUFFER 7 5 6 7 14 13 12 Q2 Q3 Q4 Q5 Q6 Q7
8
REGISTER STAGE 8 CLOCK CLOCK
LATCH 8 STROBE STROBE CLOCK
3-STATE BUFFER 8
11
Q8
10 CLOCK
QS
3
CLOCK 1
*
CLOCK CLOCK STROBE STROBE *Input Protection Diodes
CLOCK
STROBE
*
CLOCK
9
QS
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5
MC14094B
DYNAMIC TIMING DIAGRAM
tWH
3
tr 50% th 50% 90% 10%
tf
CLOCK tsu
2
DATA IN tWL
1
STROBE
15
OUTPUT ENABLE
50% tPLH 90% 10% tTHL tPHL 90% 10% tPLH 50% tPLH tPLH tPHZ 90% 10% tPHL 50% tPZH tPLZ
50% tPZL 90% 10%
N
Q1 Q7 tTLH
9
QS
tPHL 50%
10 QS
50%
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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6
MC14094B
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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7
CCC EE CCC EE
9
-W-
MC14094B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14094B/D

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